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ESS Technology, Inc.
DESCRIPTION
The ES6028 Vibratto DVD processor is a single-chip MPEG video decoder that integrates a state-of-the-art 480-pixel progressive scan video feature to provide brilliant and sharp, flicker-free output to the video display. Th e E S 6 0 2 8 p e r f o r m s a u di o / v i d e o s t r e a m d a ta processing, and TV encoding, and includes four video DACs, Macrovision copy protection, DVD system navigation, system control and housekeeping functions. The Vibratto DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia Processor (PMP) core consisting of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature set. The processing units enable simultaneous parallel execution of system commands and data processing to perform specialized encoding and decoding tasks in the device architecture. The RISC processor, and its associated hardware, perform bit stream parsing, control audio data output, transfer video and audio data to the vector engine and service system control and housekeeping functions. The vector engine (DSP), and associated hardware, perform audio and video micro-code processing required by A/V standards, such as Dolby(R) Digital, DTS surround, MPEG, and JPEG imaging. These processing tasks include audio processing, video motion compensation and estimation, loop filtering, discrete cosine transforms (DCT) and inverse DCT, quantization, and inverse quantization. The Vibratto DVD processor supports both parallel and serial DVD loader interfaces, industry standard I2S audio data input and output, EPROM and SDRAM access, and audio/video data buffering. The Vibratto also supports both letterbox and pan-and-scan displays, sub-picture overlay, and On-Screen Display (OSD). A new feature found with the Vibratto DVD solution is the ESS Music SlideshowTM, which allows a user to do voiceovers while viewing JPEG images, Kodak(R) PictureCD, and Fujicolor(R) CD images. In addition, the Vibratto DVD solution offers support for SACD, Karaoke CD+G, MP3, HDCD, CD-DA, and Windows Media Audio (WMA) decoding and playback. The ES6028 Vibratto DVD processor is available in 208pin Plastic Quad Flat Pack (PQFP) device package.
ES6028 Vibratto DVD Processor Product Brief
FEATURES
* Single-chip DVD processor based on ESS proprietary
dual CPU PMP core.
* Integrated NTSC/PAL encoder. * Progressive scan video output for flicker-free video
display.
* * * * * *
Four integrated 10-bit video DACs. DVD-Video, VCD 1.1, 2.0, and SVCD. 5.1 channel audio outputs. Interface for ATAPI devices and A/V DVD loaders. Interface for CF, MS, and SM memory cards. Direct interface of 8-/16-bit SDRAM up to 128-Mb capacity. Flash EPROM for up to 16-MB capacity.
* Direct interface for up to 4 banks of 8-/16-bit EPROM or * Macrovision 7.1 for NTSC/PAL interlaced video. * Macrovision AGC 1.03-compliant for 480p progressive
scan video.
* Composite video, S-video, YUV and RGB outputs. * 8-bit CCIR 601 YUV 4:2:2 output. * On-Screen Display (OSD) controller with 3-bit blending
provides display with 256 colors in 8 degrees of transparency.
* Subpicture Unit (SPU) decoder supports karaoke lyric,
subtitles, and EIA-608 compliant Line 21 Captioning.
* Dolby Digital (AC-3), Dolby Pro Logic, and Dolby Pro
Logic II.
* * * * * * * *
DTS surround. S/PDIF digital audio output. High-Definition Compatible Digital (HDCD) decoding. SRS TruSurround(R). Windows Media Audio. MP3. CD-DA. Karaoke.
ESS Technology, Inc.
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VEE HA2/AUX4[4] VEE I2CDATA/AUX0 I2C_CLK/AUX1 AUX2/IOW# VSS VEE AUX3/IOR# AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC LCS0# LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VEE VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VEE LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VEE CAMIN0 CAMIN1 LA0 LA1 LA2 LA3 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
ES6028 PINOUT DIAGRAM
The device pinout for the ES6028 is shown in Figure 1.
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ES6028
Figure 1 ES6028 Device Pinout
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VEE VSS DSCK DQM DCS0# VEE VSS DCS1# DB15 DB14 DB13 DB12 VEE VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VEE DMBS1 DMBS0 DRAS# DWE# DOE#/DSCK_EN DCAS# VEE VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VEE DMA5 DMA4 DMA3 DMA2 DMA1 DMA0
VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VEE TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL2 TSD0/SEL_PLL0 VSS VCC TSD1/SEL_PLL1 TSD2 NC MCLK TBCK SPDIF/PLL3 NC VSS VCC RSD RWS RBCK NC XIN XOUT AVEE AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VSS HA1/AUX4[3] HA0/AUX4[2] HCS3FX#/AUX3[6] HCS1FX#/AUX3[7] HIOCS16#/CAMCLK/AUX3[4] HRD#/DCI_ACK#/AUX4[6] HWR#/DCI_CLK/AUX4[5] VEE VSS HIORDY/AUX3[3] HRST#/AUX3[5] HIRQ/DCI_ERR#/AUX4[7] HRRQ#/AUX4[0] HWRQ#/DCI_REQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC VSS HD13/AUX2[5]/SP HD12/AUX2[4]/C2PO HD11/AUX2[3]//IRQ HD10/AUX2[2] HD9/AUX2[1] HD8/DCI_FDS#/AUX2[0]/VFD_CLK HD7/DCI7/AUX1[7]/VFD_DIN VEE VSS HD6/DCI6/AUX1[6]/VFD_DOUT HD5/DCI5/AUX1[5] HD4/DCI4/AUX1[4] HD3/DCI3/AUX1[3] HD2/DCI2/AUX1[2] HD1/DCI1/AUX1[1] HD0/DCI0/AUX1[0] VCC VSS HSYNC#/CAMIN7/AUX3[0] VSYNC#/CAMIN6/AUX3[1] PCLKQSCN/CAMIN5/AUX3[2] PCLK2XSCN/CAMIN4 YUV7/CAMIN3 YUV6/VDAC YUV5/YDAC ADVSS ADVEE YUV4/RSET YUV3/COMP YUV2/CDAC YUV1/VREF YUV0/CAMIN2/UDAC DCLK
ES6028 PRODUCT BRIEF
ES6028 PINOUT DIAGRAM
ESS Technology, Inc.
ES6028 PRODUCT BRIEF ES6028 PIN DESCRIPTION
ES6028 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6028. Table 1 Name ES6028 Pin Description Pin Numbers 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 2-7, 10-16, 19-23, 204-207 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 9, 35, 44, 83, 121, 139, 172 24 I/O Definition
VEE
P
I/O power supply.
LA[21:0]
O
RISC port address bus.
VSS
G
Ground.
VCC RESET# TDMDX
P I O I
Core power supply. Reset input, active-low. TDM transmit data output. LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k resistor; read only during reset. RSEL 0 1 Selection 16-bit ROM 8-bit ROM
RSEL
25
TDMDR TDMCLK TDMFS TDMTSC# TWS
28 29 30 31
I I I O O I
TDM receive data input. TDM clock input. TDM frame sync input. TDM output enable. Audio transmit frame sync output. System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read only during reset. SEL_PLL2 0 SEL_PLL1 0 0 1 1 0 0 1 1 SEL_PLL0 Clock Type 0 1 0 1 0 1 0 1 DCLK x 4.25 Reserved Bypass mode DCLK x 3.75 DCLK x 4.5 Reserved DCLK x 3.5 DCLK x 4
SEL_PLL2
32
0 0 0 1 1 1 1
ESS Technology, Inc.
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ES6028 PRODUCT BRIEF ES6028 PIN DESCRIPTION Table 1 Name TSD0 33 SEL_PLL0 TSD1 36 SEL_PLL1 TSD2 NC MCLK TBCK SPDIF 37 38, 42, 48 39 40 I O -- I/O I/O O I Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data output 2. No connect pins. Leave open. Audio master clock for audio DAC. Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). S/PDIF output. Clock source select. Strapped to VCC or ground via 4.7-k resistor; read only during reset. SEL_PLL3 0 1 RSD RWS RBCK XIN XOUT AVEE AVSS DMA[11:0] DCAS# DOE# 70 DSCK_EN DWE# DRAS# DMBS0 DMBS1 DB[15:0] DCS[1:0]# DQM DSCK 71 72 73 74 77-82, 85-90, 93-96 97,100 101 102 O O O O O I/O O O O DRAM clock enable. DRAM write enable. DRAM row address strobe. SDRAM bank select 0. SDRAM bank select 1. DRAM data bus. SDRAM chip select. Data input/output mask. Output clock to SDRAM. 45 46 47 49 50 51 52 53-58, 61-66 69 I I I I O P G O O O Clock Source Crystal oscillator DCLK input I O Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data output 1. ES6028 Pin Description (Continued) Pin Numbers I/O O Definition Audio transmit serial data output 0.
SEL_PLL3
41
Audio receive serial data. Audio receive frame sync. Audio receive bit clock. 27-MHz crystal input. 27-MHz crystal output. Analog power for PLL. Analog ground for PLL. DRAM address bus. DRAM column address strobe. DRAM output enable.
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ES6028 PRODUCT BRIEF ES6028 PIN DESCRIPTION Table 1 Name DCLK YUV0 CAMIN2 ES6028 Pin Description (Continued) Pin Numbers 105 I/O I O I O Definition Clock input to PLL. YUV pixel 0 output data. Camera input 2. Video DAC output. Pin Value 0 1 2 3 4 5 UDAC 106 6 7 8 9 10 11 12 13 114 DAC V CVBS1 CVBS1 N/A CVBS1 CVBS1 CVBS1 N/A SYNC CHROMA CVBS1 CVBS1 SYNC N/A CVBS1 113 DAC Y Y Y Y N/A N/A Y Y G Y G G G Y Y 108 DAC C C C C N/A N/A Pb Pb B Pb B R R Pr Pr 106 DAC U N/A CVBS2 N/A CVBS2 N/A Pr Pr R Pr R B B Pb Pb
Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. YUV1 107 VREF YUV2 108 CDAC YUV3 109 COMP YUV4 110 RSET ADVEE ADVSS 111 112 I P G DAC current adjustment resistor input. Analog power for video DAC. Analog ground for video DAC. I O Compensation input. Bypass to ADVEE with 0.1-F capacitor. YUV pixel 4 output data. O O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 3 output data. I O Internal voltage reference to video DAC. Bypass to ground with 0.1-F capacitor. YUV pixel 2 output data. O YUV pixel 1output data.
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ES6028 PRODUCT BRIEF ES6028 PIN DESCRIPTION Table 1 Name YUV5 113 YDAC YUV6 114 VDAC YUV7 115 CAMIN3 PCLK2XSCN 116 CAMIN4 PCLKQSCN CAMIN5 AUX3[2] VSYNC# CAMIN6 AUX3[1] HSYNC# CAMIN7 AUX3[0] HD[5:0] DCI[5:0] AUX1[5:0] HD6 DCI6 128 AUX1[6] VFD_DOUT HD7 DCI7 131 AUX1[7] VFD_DIN HD8 DCI_FDS# 132 AUX2[0] VFD_CLK HD9 133 AUX2[1] I/O Aux2 data I/O. I/O I I/O Aux2 data I/O. VFD clock input. Host data bus line 9. I/O I I/O I/O Aux1 data I/O. VFD data input. Host data bus line 8. DVD input sector start. I/O I I/O I/O Aux1 data I/O. VFD data output. Host data bus line 7. DVD channel data I/O. 122-127 119 118 117 I O I I/O I/O I I/O I/O I I/O I/O I/O I/O I/O I/O Camera YUV 4. 13.5-MHz video output pixel clock. Camera YUV 5. Aux3 data I/O. Vertical sync, active-low. Camera YUV 6. Aux3 data I/O. Horizontal sync, active-low. Camera YUV 7. Aux3 data I/O. Host data bus lines 5:0. DVD channel data I/O. Aux1 data I/O. Host data bus line 6. DVD channel data I/O. I I/O Camera YUV 3. 27-MHz video output pixel clock. O O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 7 output data. O O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 6 output data. ES6028 Pin Description (Continued) Pin Numbers I/O O Definition YUV pixel 5 output data.
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ES6028 PRODUCT BRIEF ES6028 PIN DESCRIPTION Table 1 Name HD10 134 AUX2[2] HD11 AUX2[3] IRQ HD12 AUX2[4] C2PO HD13 AUX2[5] SP HD14 140 AUX2[6] HD15 AUX2[7] IR HWRQ# DCI_REQ# AUX4[1] HRRQ# 143 AUX4[0] HIRQ DCI_ERR# AUX4[7] HRST# 145 AUX3[5] HIORDY 146 AUX3[3] HWR# DCI_CLK AUX4[5] HRD# DCI_ACK# AUX4[6] 150 149 I/O I/O I/O I/O O O I/O Aux3 data I/O. Host write. DVD channel data clock. Aux4 data I/O. Host read. DVD channel data valid. Aux4 data I/O. I/O I Aux3 data I/O. Host I/O ready. 144 I/O I/O I/O I/O O Aux4 data I/O. Host interrupt. DVD channel data error. Aux4 data I/O. Host reset. 142 141 I/O I/O I/O I O O I/O O Aux2 data I/O. Host data bus line 15. Aux2 data I/O. IR remote control input. Host write request. DVD control interface request. Aux4 data I/O. Host read request. 137 136 135 I/O I/O I/O O I/O I/O I I/O I/O I I/O Aux2 data I/O. Host data bus line 11. Aux2 data I/O. IRQ. Host data bus line 12. Aux2 data I/O. C2PO error correction flag from CD-ROM. Host data bus line 13. Aux2 data I/O. 16550 UART serial port input. Host data bus line 14. ES6028 Pin Description (Continued) Pin Numbers I/O I/O Definition Host data bus line 10.
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ES6028 PRODUCT BRIEF ES6028 PIN DESCRIPTION Table 1 Name HIOCS16# CAMCLK AUX3[4] HCS1FX# 152 AUX3[7] HCS3FX# 153 AUX3[6] HA[2:0] 154, 155, 158 AUX4[4:2] AUX0 160 I2CDATA AUX1 161 I2C_CLK AUX2 162 IOW# AUX3 165 IOR# AUX7-4 LOE# LCS[3:0]# LD[15:0] LWRLL# LWRHL# CAMIN0 CAMIN1 166-169 170 173-176 178-182, 185-191, 194-197 198 199 202 203 O I/O O O I/O O O I I I/O Read strobe (LCS1). Auxiliary ports. RISC port output enable. RISC port chip select. RISC port data bus. RISC port low-byte write enable. RISC port high-byte write enable. Camera YUV 0. Camera YUV 1. O I/O I/O Write strobe (LCS1). Auxiliary port. I/O I/O I2C clock I/O. Auxiliary port. I/O I/O I2C data I/O. Auxiliary port 1 (open collector). I/O I/O Aux4 data I/Os. Auxiliary port 0 (open collector). I/O I/O Aux3 data I/O. Host address bus. I/O O Aux3 data I/O. Host select 3. 151 ES6028 Pin Description (Continued) Pin Numbers I/O I I I/O O Definition Device 16-bit data transfer. Camera port pixel clock input. Aux3 data I/O. Host select 1.
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ESS Technology, Inc.
ES6028 PRODUCT BRIEF SYSTEM BLOCK DIAGRAM
SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES6028 Vibratto DVD player board design is shown in Figure 2.
Video ROM/Flash Audio SDRAM 4/16 MB EEPROM Audio DAC S/PDIF Audio Audio ADC VFD Driver
TV Display
Speakers A/V Receiver Microphone In VFD Panel IR Remote
ES6028 Vibratto
DVD Drive
Figure 2 ES6028 Vibratto System Block Diagram
ESS Technology, Inc.
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ES6028 PRODUCT BRIEF ORDERING INFORMATION
ORDERING INFORMATION
Part Number ES6028F Description Vibratto 5.1-channel DVD, DTS, Progressive Scan and TV Encoder Package 208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP.
Other Vibratto DVD Processors
Part Number ES6008F ES6018F ES6038F Description Vibratto 2-channel DVD and TV Encoder Vibratto 5.1-channel DVD, DTS and TV Encoder Vibratto 5.1-channel DVD, DTS, Progressive Scan, DVD-Audio and TV Encoder Package 208-pin PQFP 208-pin PQFP 208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP.
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/IEC. References to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee draft ISO 11172 dated January 9, 1992. VideoDrive and Vibratto are trademarks of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of SRS Labs, Inc. All other trademarks are trademarks of their respective companies and are used for identification purposes only.
ESS Technology, Inc. 48401 Fremont Blvd. Fremont, CA 94538 Tel: (510) 492-1088 Fax: (510) 492-1898
10 http://www.esstech.com
ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.
(c) 2004 ESS Technology, Inc.
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